Many electronic systems use integrated circuits that employ one of the several IC fabrication technologies that are susceptible to a failure mechanism called latchup. Latchup is a metastable electrical state into which an IC, can be triggered by the unintended action of parasitic circuit elements which are structurally inherent in these chips. It can be initiated either by electrical means, or by exposure to transient ionizing radiation. The former method is a matter of concern to all users of ICs, while the latter is a matter of special concern to systems which may be exposed to nuclear radiation, such as military systems or commercial space systems. Designers of all systems for which high reliability is important want to harden them against the failure mechanism of latchup.
Moreover, as previously noted in general terms, latchup is a metastable electrical state into which an integrated circuit can be excited by the unintended action of parasitic circuit elements. It results from positive feedback between two bipolar transistors, an explicit circuit transistor and a parasitic transistor, or two parasitic transistors, built into the integrated circuit. When two such devices are interconnected in a positive feedback configuration as shown in FIG. 1(a), they can give rise to an “S” type negative resistance characteristic between the voltage supply and ground, also shown in FIG. 1. This configuration can be biased stably at either of two points where a load line intersects the “S” characteristic in a region of positive slope. In normal operation, CMOS ICs are biased in Region I, called the forward blocking region. If an IC is excited into a state where it is biased into Region II in FIG. 1, normal circuit operation is prevented as long as it remains in Region II.
Modern integrated circuits (ICs) consist of many silicon transistors (in some cases, a million or more), manufactured in one piece of silicon, which is usually electrically conductive. Some method of achieving electrical isolation between these many devices is needed, to prevent undesired electrical interconnection. Since the birth of integrated circuit technology, a number of schemes have been proposed for isolating the different devices in ICs. One of the earliest methods advanced is the one that is still the most widely used, viz. “junction isolation”. In this method, the isolation is provided by a reverse-biased P-N junction, formed between the silicon starting material and a region or regions in which are devices to be electrically isolated from other regions. Junction isolation is used both in ICs which use bipolar transistor technology and those that use field effect transistor technology (e.g. complementary metal oxide semiconductor, or CMOS, technology). CMOS is the most widely used technology currently in production, so the examples given here will cite examples of CMOS ICs but the concepts apply to any type of IC which uses junction isolation technology.
CMOS is the name applied to an integrated circuit technology that uses both P- and N-channel field effect transistors (FETs) in the same chip. To build P- and N-channel FETs, it is necessary to have both N and P type background material. This is accomplished by starting with a silicon wafer of one type (e.g. P type) and creating in it regions of the opposite type by ion implantation, diffusion, or some other means of doping the starting material in selected areas. The regions where the silicon starting material has been counterdoped to form background material of the opposite conductivity type are known as wells or tubs.
FIG. 2 shows a cross sectional view of the PMOS and NMOS transistors that are used in an inverter, which is a common, frequently used circuit in CMOS ICs. FIG. 2 shows how these structures are biased to obtain electrical isolation between NMOS devices built in the P-type substrate (starting material), and the PMOS devices built in an N-well. (This implementation of CMOS is called N-well CMOS. Other implementations of CMOS are possible, viz. P-well CMOS, in which the starting material is N-type, and a P-type well is formed in the starting material, and twin well CMOS, in which both an N-type well and a P-type well is formed in the starting material, and PMOS devices are formed in the former, while NMOS devices are formed in the latter.)
In the N-well configuration shown in FIG. 2, the reverse biased P-N junction existing between the N-well and the P-type substrate presents a high impedance between these regions, permitting the PMOS device to be biased independently of the NMOS device. Junction isolation technology works very well, and has been used in the vast majority of all integrated circuits ever built. Unfortunately, however, the additional junction, whose only function is to isolate different devices within the IC, introduces, unintentionally, a number of parasitic devices. FIG. 3 shows that the simple CMOS circuit shown in FIG. 2, as implemented in N-well CMOS, has two lateral bipolar NPN transistors LT1, LT2 (denoted as LNPN in FIG. 4) and two vertical bipolar PNPs VT1, VT2 (denoted as VPNP in FIG. 4) associated with it, as well as eight distributed resistors. Similar parasitic transistors exist in P-well and twin well CMOS ICs. These parasitic transistors are normally in an inoperative state, and play no role in the operation of the IC other than isolating different devices. However, they are connected in a configuration similar to that of a four layer diode, i.e. a PNPN configuration. As such, they are capable of being triggered into a state that interferes with the correct operation of the IC. This triggering can occur either by applying the chip bias in an incorrect sequence, by a voltage on an output terminal suffering from an overshoot or undershoot, or by transient currents generated by ionizing radiation. This state, which can be self-sustaining until the power supply is cycled OFF and ON again, is called latchup.
Latchup triggering is the process by which the parasitic devices are switched from the blocking state to “ON” state. Several conditions have been stated as necessary before switching can occur.                1. The loop gain of the PNPN configuration must exceed unity. (Recent research has indicated that this may not be required.)        2. Current through the blocking junction must reach the level defined as the switching current. Turn-on is usually caused by externally excited current flow through one or both emitter/base bypass resistors.        3. The bias supply must be capable of supplying the necessary current.        
The first condition for latchup cited above relates to the properties of the two parasitic bipolar transistors. In the static case, this condition is equivalent to the requirement that the sum of the forward common base current gains of the two transistors must exceed unity, i.e.αNPN+αPNP≧1  Eqn. 1This condition is overly restrictive when applied to the triode or tetrode configurations, and overly generous for the dynamic situation. Recent studies have refined the requirements on loop gain to include the triode and tetrode cases, and both the static and dynamic latchup cases, but Eqn. 1 has the benefit of simplicity, and shall be used in this document to describe semi-quantitatively the method of latchup suppression of the present invention.
The common base current gain (alpha) of the parasitic bipolar transistors found in CMOS integrated circuits is a complex function of the topology of the structures and the fabrication process(es) used to build them. Factors controlling the values of alpha encountered in practical ICs are discussed below.
In the N-well CMOS configuration being discussed herein, the NPN parasitic bipolar device is a lateral transistor, i.e., minority carriers (electrons in this example) injected into the P-type substrate from an N-type contact diffuse laterally (parallel to the silicon surface) through the P-type substrate, serving as the base of the bipolar device, and are collected by the N-well. One of the N-type diffusions used as a source or drain of an NMOS device serves as the emitter of this parasitic transistor and the N-well serves as the collector. The current gain of this device is given by:αNPN=γ1,NPNγ2,NPN  Eqn. 2Where:γ1,NPN is the emitter injection efficiency, i.e. the efficiency with which the emitter injects minority carriers into the base region. It is a function of the ratio of the majority carrier density in the emitter to that in the substrate, approaching one as this ratio gets large and γ2 NPN is the base transport probability, i.e. the probability that a minority carrier injected into the P-type substrate by the emitter can travel to the N-well before recombining with a majority carrier, thereby being annihilated. It is a function of the ratio between the distance from the emitter to the N-well and the average distance, Ln, which a minority carrier can diffuse before recombining.
The spacing between diffused regions and the isolation well in CMOS ICs is being made smaller and smaller as technology advances, with the result that the gain of lateral devices is becoming more of a problem. The minority carrier diffusion length, L, is a function of the density of recombination centers such as crystal defects. (The method for suppressing latchup according to the present invention involves a procedure which increases the density of such defects locally to degrade L, and hence degrade the current gain of the parasitic lateral bipolar transistor.)
In the N-well CMOS configuration being discussed herein, the PNP parasitic bipolar device is a vertical transistor, i.e. minority carriers injected into the N-well by one of the P-type diffusions flow vertically (normal to the silicon surface) through the N-well serving as the base of this device, and are collected by the substrate. A P-type diffusion used as a source or drain of a PMOS device serves as the emitter of this parasitic transistor, the N-well serves as the base region, and the substrate serves as the collector. The current gain of this device is given by:αPNP=γ1,PNPγ2,PNP  Eqn. 3Where:γ1,PNP is the emitter injection efficiency, i.e. the efficiency with which the emitter injects minority carriers into the base region. It is a function of the ratio of the majority carrier density in the emitter to that in the substrate, approaching one as this ratio gets large and γ2,PNP is the base transport probability, i.e. the probability that a minority carrier injected into the N-well can travel to the substrate before recombining with a majority carrier, thereby being annihilated. It is a function of the ratio between the distance from the emitter to the substrate, and the average distance, Lp, which a minority carrier can diffuse before recombining. The isolation well depth in CMOS ICs is being made smaller and smaller as technology advances, with the result that the gain of vertical devices is becoming more of a problem. The minority carrier diffusion length, Lp, is a function of the density of recombination centers such as crystal defects.
To initiate latchup in CMOS ICs, lateral current flow is required to turn on the parasitic devices. Various excitations can produce lateral current flow and trigger latchup if sufficiently large. These modes can be divided into three types, viz.
Type 1: External Initiation of First Bipolar
In Type 1 triggering, some excitation has turned on the first bipolar transistor, usually an overshoot or undershoot at an input and/or an output node of the IC. Latchup follows if the second transistor is turned on by the first, and if the total current into the parasitic PNPN reaches the switching current for the particular PNPN triode structure that results when the bypass resistor on the first transistor is removed. Latchup is sustained if the total current has also reached the switching current for the full tetrode structure. If the total current lies between the switching currents for the two configurations, latchup is temporary, and the PNPN device returns to the blocking state once the external source is removed.
Type 2: Normal Bypass Current Initiation of Both Bipolars
In Type 2 triggering, the excitation causes current to flow through both bypass resistors. The excitation in this case is usually avalanche current, photocurrent, or displacement current through the well/substrate junction. Usually the transistor with the larger bypass resistor turns on first. For latchup to occur, the second transistor must also turn on, and PNPN current must reach the switching current as calculated for the full tetrode configuration. Latchup is then always sustained.
Type 3: Degraded Bypass Current Initiation of Both Bipolars
In Type 3 triggering, the excitation has already degraded the blocking state by creating a lower impedance path. This path is between the power supply and ground or between power supply and substrate supply, in the case of punchthrough or a field FET device. In the case of source/drain avalanche, it is between the power supply and a signal line or between a signal line and the substrate supply. In this case, the first transistor is not exhibiting bipolar transistor action, but is supplying current that, if large enough, can turn on the second transistor. At least temporary latchup occurs once the PNPN current has reached the switching current calculated for the triode configuration formed by removing the excited transistor's bypass resistor. Whether latchup is sustained depends on the same set of conditions as for Type 1 triggering.
FIG. 5 summarizes turn-on sequences leading to latchup for the various excitations for N-well CMOS.
The static requirements on the current supply which must be met for latchup to occur are obvious. A sufficient switching current must be available for the parasitic circuit to leave the blocking state and the supply must be capable of supplying the holding current, III, for the parasitic circuit to reach the “ON” state. In addition to these requirements, however, the actual triggering waveform is important for understanding whether latchup occurs. Because of finite base transit times and possible RC time constant limits of applied pulses, any excitation must be applied for a critical length of time, which is the time to bring the PNPN device current up to the switching current. Excitation applied for a shorter time, regardless of its magnitude, does not cause latchup.
In normal operation, the circuit shown in FIG. 2 would exhibit a high impedance current-voltage characteristic between the supply and ground. If it is triggered into the latchup state, and if the latchup persists' after the triggering condition is removed, the latchup is described as self-sustaining. If this occurs, the chip current-voltage characteristic switches to a low impedance region. FIG. 1 shows a representative current-voltage characteristic for a CMOS integrated circuit, showing the high impedance region (Region I, Forward blocking region) and the low impedance region (Region II, ON Region).
If the power supply is stiff, i.e. if it maintains its output voltage despite high load current, the power supply will push high currents through the chip, since the impedance which the chip presents to the power supply in Region II is very low. These high currents can easily exceed the current for which the chip was designed, and the chip metallization may suffer burnout. This would represent permanent failure.
If the power supply is not stiff, and the voltage across the chip drops due to the high current drain, the circuitry on the chip will not be able to operate because of low voltage. This can be corrected by turning off the power to the chip, and then turning the chip ON again. This is called “toggling” the latch. It removes the current from the parasitic bipolar transistors, and when voltage is re-applied, they return to the high impedance state, permitting the chip to resume operation. If the voltage across the chip drops below VH, the circuit will toggle itself, and will return to the high impedance state, permitting renewed operation without external assistance.
In either of the first two cases, a loss of circuit function occurs as a result of the latchup. In the first case, a permanent failure results. In the second case, the loss of functionality is temporary, but requires intervention to overcome the failure. In the third case, the circuit recovers without intervention. However, this case is still problematic, because the CMOS integrated circuit will not function for some period of time during which the minority carrier concentration in the parasitic elements returns to normal. Any of these cases would be very serious in many applications, and users want chips that are incapable of latchup.
The present invention as described herein comprises a post-manufacturing step that can be performed, either at the wafer level or the die level, to reduce or even eliminate latchup sensitivity of ICs. In these regards, the susceptibility of CMOS integrated circuits to certain types of latchup could be significantly reduced if the properties of silicon which control the initiation of photocurrent (a type of normal bypass current discussed under the Type 2 triggering mode) could be degraded, or if the properties of silicon which control the current gain of the parasitic bipolar transistors could be degraded, without degrading the functional properties of the CMOS circuit in either case. The above discussion of latchup shows that the physical processes involved in these types of latchup take place near, but somewhat below, the front surface of the chip. On the other hand, the physical processes involved in MOS transistor operation on which the functional operation of the integrated circuit is based, take place at the front surface of the chip. The difference in the location at which the primary function of the integrated circuit is centered and that at which the parasitic devices operate provides the basis for suppressing latchup without degrading the electrical properties of the integrated circuit.
According to the present invention, ion implantation is a process technique that permits the properties of silicon to be changed in a highly controlled and highly localized manner. Ion implantation is the introduction of ionized atoms into targets with enough energy to penetrate beyond surface regions. The most common application is the doping of silicon during device fabrication. The use of 3- to 500 keV energy for boron, phosphorous, or arsenic dopant atoms is sufficient to implant the ions from about 100 to 10,000 angstroms below the silicon surface. The silicon is annealed after implanting the dopant atoms by heating to elevated temperatures of approximately 600° C. to 1000° C. Annealing decreases the crystalline damage introduced by the implantation process, and causes most of the implanted ions to take substitutional positions in the silicon crystal lattice. This permits the use of ion implantation as a means for introducing dopant atoms into semiconductors.
The present invention deals with a different way to use ion implantation. For purposes of this discussion, it will be assumed that the silicon has already completed the normal production process, and that the finished wafer (or die) can no longer be exposed to temperatures as high as those used in annealing without destroying the device. Furthermore, since the front surface of the chip contains the operational portions of the integrated circuit, ion implantation through this surface would not be desirable. Yet it is desirable to change the properties of the silicon close to the front surface of the chip. Consequently, the present invention deals with the implantation of atoms through the back surface with an energy sufficient to penetrate to a position close to the front surface. There, the atoms can change those properties of the silicon that control the generation and/or collection of photocurrent and the properties of silicon that control the current gain of the parasitic bipolar transistors, yet not cause any significant damage to the front surface of the chip. These changes depend on the chemical and electronic properties of the implanted ions (whether they are inert, such as helium, argon, etc.) or are electronically active (such as metal atoms) or are chemically active (such as oxygen, nitrogen, etc.). They also depend on where the implanted ions come to rest in the target, and the amount of crystalline damage they do in coming to rest.
An individual implanted ion undergoes scattering events with electrons and atoms in the target, reducing the ion's energy until it either leaves the target or comes to rest. The particular loss mechanism is a function of the energy of the ion, E, with electronic interaction prevailing at high energy, and nuclear stopping predominating at low energies. In the present invention we deal with cases where the ion has a high energy when it enters the target material, but loses all of its initial energy and is stopped in the target. In such cases, the primary energy loss mechanism initially is electronic interactions. As the ion slows down, nuclear stopping takes over. The energy loss per unit path length of penetration into the target is called the stopping power. FIG. 6 shows Bragg curves of stopping power for alpha particles and protons in silicon, using as the abscissa the distance remaining to the end of the particle path. Similar curves describe the stopping power of heavier ions, as well.
The total path length of the ion is called the range, R. A typical ion stops at a distance normal to the surface into which the implantation occurs called the projected range, Rp. Some ions are statistically lucky, and encounter fewer scattering events in a given distance, and so come to rest beyond the projected range. Other ions are unlucky, and have more than the average number of scattering events. These atoms come to rest between the surface and the projected range. The fluctuation in the projected range is called the straggle, delta Rp. There is also a fluctuation in the final ion's position perpendicular to the incident ion's direction, called the lateral straggle, delta Rlateral.
The range of ions in solids is determined by the LSS theory [J. Lindhard, M. Scharff, and H. Schiott, “Range Concepts and Heavy Ion Ranges”, Mat.-Fys. Med. Dan. Vid. Selsk, 33, No. 14, 1 (1963)]. Based on this theoretical treatment, the probability of scattering events can be determined and used in Monte Carlo computer codes to determine the profiles of implanted atoms. Alternatively, several analytical expressions have been derived for approximating the depth distribution of implanted ions.
An important feature of ion implantation is the fact that the density of implanted atoms maximizes at Rp, with almost all the implanted atoms being found within a distance of three times delta Rp from the range, Rp. This means that ion implantation is an ideal method for putting a controlled amount of an ion at a specific location in a semiconductor. FIG. 7 shows a boron implanted atom profile, with measured data points, four-moment analytical and symmetric Gaussian curves. It can be seen that the forward edge of the implanted profile of boron, (implanted at 800 keV), which is the region of greatest interest this invention, is very well described by both the four-moment and the symmetric Gaussian curves. Profiles for heavier ions (e.g. arsenic) show skewness on the deep side of the implant profile.
As stated above, the ions being implanted lose energy to the target by two types of interactions. First, they have collisions with electrons in target atoms which create electron excitations. The energy lost by the ions in such interactions is subsequently transferred to phonons, which heats the target but produces no permanent damage. The second type of collision displaces target atoms from their original positions. This type of interaction can produce permanent damage to the target, and is one of the types of interaction which this invention exploits.
When a target atom is hit by an ion, a recoil cascade is started. The recoil atom can then collide with other target atoms, generating a number of displacement and replacement collisions, creating vacancies and leaving atoms that participate in the cascade in interstitial positions. (A vacancy is the hole left behind when a recoil atom moves from its original site. An interstitial atom is one that is left in a crystalline position not normally occupied by target atoms.) Vacancies and interstitial atoms of the target material can remain after the ion implantation is completed, and can produce changes in the electronic properties of the target material. In particular, they can serve as trapping and/or recombination centers, degrading both the majority carrier properties and minority carrier properties of semiconductors.
There are three approaches, utilizing ion implantation through the back surface of an integrated circuit, that can be pursued to suppress latchup. The first reduces current flow through one or both emitter/base resistors that arises due to photocurrent across the well junction. Degrading the minority carrier lifetime near the well junction will reduce the photocurrent, and thus reduce the likelihood that latchup will occur. The second approach reduces the voltage drop that a given amount of current across the well junction will produce in the junctions of the parasitic bipolar devices by increasing the conductivity of the silicon. This is accomplished by implanting ions which are electrically conducting near the well junction. The third approach degrades the common base current gain of one or both of the two parasitic bipolar transistors so that the loop gain of the PNPN configuration can not exceed unity. This is done by exploiting the crystalline damage that results from ion implantation. The current gain of the parasitic transistors is degraded by reducing the minority carrier lifetime in the base region of these devices, which occurs as a result of crystalline damage from ion implantation.
Generation of photocurrent in semiconductors such as silicon requires the flow of both minority and majority carriers. The ability to collect minority carriers depends on the distance that a minority carrier can travel before recombining with a majority carrier (the minority carrier diffusion length, L). The minority carrier diffusion length is a function of the density of recombination centers such as crystal defects. The method for suppressing latchup proposed herein involves a procedure which increases the density of such defects locally to degrade L, and hence degrade the photocurrent that will be generated by a given radiation exposure.
FIGS. 3, 4 and 5 show the role played by the resistances in the circuit containing the parasitic bipolar transistors. In every case, the voltage drops across these resistances play a substantial role in causing latchup. If these resistances could be reduced in magnitude, either a larger current would be required to induce latchup, or latchup could be avoided altogether. The implantation of metallic atoms is a method of reducing these resistance which is compatible with the post-production procedure described in this invention. If the implanted ions are metallic, they will supply charge carriers which can reduce the resistance and thereby reduce the voltage drop across the emitter-base junctions of these parasitic transistors.
The current gain of a bipolar transistor depends on the probability that a minority carrier injected into the base of such a device can travel to the collector before recombining with a majority carrier, thereby being annihilated. It is a function of the ratio between the width of the base and the average distance, L, which a minority carrier can diffuse before recombining. The minority carrier diffusion length is a function of the density of recombination centers such as crystal defects. The method for suppressing latchup proposed herein involves a procedure which increases the density of such defects locally to degrade L, and hence degrade the current gain of one or both parasitic bipolar transistors.